1. Field of the Invention
The present invention relates to a nonvolatile memory cell and a method of producing the same. More particularly, the present invention relates to a electrically rewritable nonvolatile memory cell which is suitable for a flash memory, and a method of producing the same.
2. Description of the Related Art
A flash memory utilizing hot electron injection for programming, and Fowler-Nordheim tunneling for erasing has been actively developed. A flash memory is a memory which is byte-electrically programmable and block-electrically erasable. FIGS. 30, 31, and 32 show a memory cell of a typical flash memory which is currently produced. The memory cell is used in NOR type flash memory or a NAND type flash memory. The construction of the memory cell is the same as that of a memory cell of an electrically programmable read only memory (EPROM). Hereinafter, a memory cell of an NOR type flash memory is described.
Referring to FIGS. 30 to 32, a nonvolatile memory cell of a conventional flash memory is described. FIG. 30 is a plan view of a conventional memory cell 50, FIG. 31 is a cross-sectional view taken along the line X31--X31 in FIG. 30, and FIG. 32 is a cross-sectional view taken along the line X32--X32. A flash memory includes a number of memory cells 50, but these figures each show only one memory cell 50 for simplicity. A control gate 56 shown in the figures functions as a control gate for a plurality of memory cells. On the other hand, a floating gate 54 is individually provided for each memory cell 50, in an electrically floating state.
The surface of a silicon substrate 51 is divided into a plurality of active regions, and element isolating regions for isolating the active regions from each other. In the element isolating region of the silicon substrate 51, as is shown in FIG. 32, a field oxide film (a LOCOS film) 52 is formed. In the active region 51a of the silicon substrate 51, as is shown in FIG. 31, a source region 60 and a drain region 61 are provided. On the active region 51a of the silicon substrate 51, a tunnel oxide film (a first insulating film ) 53 made of SiO.sub.2, a floating gate 54, an oxide-nitride-oxide (ONO) insulating film (a second insulating film) 55, and a control gate 56 are successively formed in this order. The control gate 56 has a polycide structure including an N.sup.+ polycrystalline silicon film 57 as a lower layer and a WSi.sub.x film 58 as an upper layer. Hereinafter, the term "polycrystalline silicon" is referred to as "poly-Si".
In the flash memory of NOR type, a bit line (not shown) which is a common line for a plurality of memory cells 50 is connected to the drain region 61 of the memory cell 50. The source region 60 itself extends as an interconnection of a diffused layer in parallel to a direction along which the control gate 56 extends. The diffused layer interconnection serves as a common interconnection (a common source region) between a plurality of memory cells 50.
In such prior art, a poly-Si film which is to be a floating gate 54 is first processed so as to have a shape extending in a traverse direction from FIG. 30, thereby obtaining a poly-Si film 64b. The poly-Si film 64b completely covers the active region of the silicon substrate 51, and covers part of the field oxide film 52. Thereafter, when a polycide film is patterned to form a control gate 56, the poly-Si film 64b is processed again so as to form a floating gate 54. As a result, the floating gate 54 is formed only in an overlapping portion of the poly-Si film 64b and the control gate 56, as is shown in FIG. 30. In this way, the position and the shape of the floating gate 54 is self-aligned with the control gate 56 as is shown in FIG. 31.
The tunnel oxide film 53 is a thermal oxide film having a thickness t1 of 8-15 nanometers (nm). The floating gate 54 is usually formed of poly-Si in which phosphorus of about 1.times.10.sup.20 /cm.sup.3 is diffused. In general, the thickness t2 of the poly-Si is in the range of about 100 to 300 nm. The ONO insulating film 55 is formed in the following manner. First, an oxide film (having a thickness in the range of about 5 to 10 nm) is obtained by thermally oxidizing the floating gate 54. On the thermal oxide film, an SiN film (having a thickness in the range of about 8-15 nm) is deposited by chemical vapor deposition (CVD). Then, an oxide film (having a thickness in the range of 5 to 10 nm) is formed by thermal oxidation or CVD. The ONO insulating film is an extremely thin film. Specifically, the total film thickness t3 of the ONO insulating film 55 is about 20 nm at the most in the equivalent oxide thickness. Instead of the ONO insulating film 55, a thermal oxide film may be used.
In the above prior art, immediately after the etching of the control gate 56, the floating gate 54 is etched. In more detail, the WSi.sub.x film 58 and the N.sup.+ poly-Si film 57 which constitute the control gate 56 are etched, so as to obtain the control gate 56 as is shown in FIG. 30. Then, the ONO insulating film 55 is etched. Thereafter, the poly-Si film 64b should be etched so as to form the floating gate 54.
As is shown in FIG. 32, a stepped portion 55a of the ONO insulating film 55 is formed on the side face of the floating gate 54. The stepped portion 55a should be completely removed in the etching step of the ONO insulating film 55. In order to entirely remove the stepped portion 55a, it is necessary to perform the etching step of the ONO insulating film 55 for a time period which is sufficient to completely etch an insulating film having a thickness at least equal to the height of the stepped portion 55a (which is equal to the thickness of the floating gate 54).
An insufficient etching of the stepped portion 55a causes the following problems. The problems are described with reference to FIGS. 33 and 34. FIG. 33 is a cross-sectional view taken along the line X33--X33 in FIG. 30. If the stepped portion 55a is insufficiently etched, the non-etched portion of the ONO insulating film 55 forms a fence 70 as is shown in FIG. 33. The fence 70 may serve as a mask, so that another fence 71 is produced as a non-etched portion of poly-Si which constitutes the floating gate.
The fence 71 of poly-Si electrically short-circuits the floating gates of a plurality of memory cells 50 adjacent to each other, and allows the electric charges in the floating gates 54 to escape. Accordingly, the production of a fence 71 must be avoided in the flash memory cell 50.
In order to remove the ONO insulating film 55 having the thickness t3 of about 20 nm, the etching step is performed for an amount corresponding to the thickness t2 of the floating gate 54. As a result, the field oxide film 52 which is not covered with the floating gate 54 and the control gate 56 is etched, so as to form a recess 52a in the field oxide film 52 as is shown in FIG. 34. Since thickness of an end portion of the field oxide film 52 is gradually reduced, a portion of the silicon substrate 51 in the element isolating region may be disadvantageously exposed due to the formation of the recess 52a in the end portion of the field oxide film 52. After the etching step of the ONO insulating film 55, an etching step of the poly-Si film is performed in order to form the floating gate 54. If the portion of the silicon substrate 51 is exposed, the exposed portion may be etched in the etching step of the poly-Si film.
In order to solve the above problem, it is necessary to form the floating gate 54 (the poly-Si film 64b) so as to overlap the field oxide film 52 with a sufficiently large width, for the purpose of preventing the thin end portion of the field oxide film 52 on the active region side from being exposed. The increase of the overlap amount corresponds to the increase of the total width of the poly-Si film 64b in FIG. 30 (i.e., the length measured along a direction in which the control gate 56 extends).
In the case of FIG. 34, one end portion of the field oxide film 52 in the traverse direction of FIG. 32 has a smooth slope at the interface with the silicon substrate 51, the angle .theta. indicating the thickness distribution of an oxide film constituting the field oxide film 52 is 45.degree., and the film thickness t2 of the floating gate 54 is 150 nm. In such a case, a necessary overlap amount L1 of the floating gate 54 (the poly-Si film 64b) on the field oxide film 52 is at least 150 nm. As a result, as compared with the case where such an overlap amount L1 is not required, the width of the memory cell 50 corresponding to the length of the memory cell 50 in the traverse direction of FIG. 32 is increased by at least 300 nm.
In most cases, the floating gate 54 exists only within the array of memory cells 50. Accordingly, the memory cell array is higher than a peripheral circuit portion by an amount of at least the floating gate 54 and the control gate 56. Therefore, a metal interconnection for connecting the memory cell array and the peripheral circuit portion is extended over the height difference between the memory cell array and the peripheral circuit portion. For this reason, an extra focus margin corresponding to the height difference is required in a photo process such as an exposure of a photomask. In order to minimize the focus margin, it is necessary to minimize the thicknesses of the floating gate 54 and the control gate 56.
In the case where the floating gate 54 and the control gate 56 are not thin, and the silicon substrate 51 is exposed to light using a photomask for forming the metal interconnection, for example, the light is focused on the memory cell but is not focused on the peripheral portion. Accordingly, the line width of the metal interconnection may be increased or varied, so that the line width of the metal interconnection cannot be formed as designed, which results in an inferior interconnection.
In order to eliminate the above problems, the poly-Si film which constitutes the floating gate 54 should be made to be thin. However, it is very difficult to grow a thin poly-Si film having a uniform thickness in the range of 40 to 50 nm on the tunnel oxide film 53. Such a thin poly-Si film may tend to cause local ultra-thin portions, so that large differences in levels can be observed microscopically. Moreover, it is very difficult to diffuse impurities in such a thin poly-Si film having a microscopically nonuniform thicknesses. The reason is that, in the case of ion implantation, the implanted ions locally pass through the poly-Si film and reach the underlying tunnel oxide film 53. This causes damage in the tunnel oxide film 53, and deteriorates the reliability of the electric insulating property. In the case where POCl.sub.3 is diffused in the poly-Si film, the phosphorous concentration is locally increased in the poly-Si film, so that the reliability of the electric insulating property of the tunnel oxide film 53 is also deteriorated.
As a fabrication method of a silicon film which constitutes the floating gate 54, a method utilizing an amorphous silicon film instead of the poly-Si film is known. Japanese Laid-Open Patent Publication No. 1-13771 describes a method in which an amorphous silicon film is deposited, and then crystallization is performed from the seed region by annealing, whereby the floating gate is formed of a single crystal silicon film. However, the above-identified publication does not mention how thick the floating gate is, whether the doping is performed or not, and the like.
Japanese Laid-Open Patent Publication No. 1-129465 describes a method in which the floating gate is formed to have a two-layer structure including a poly-Si film and an amorphous silicon film. In this prior art, the amorphous silicon film has a thickness of several tens of nanometers, and the poly-Si film is thicker than the amorphous silicon film. After the two-layer structure is formed, phosphorus is thermally diffused.
Japanese Laid-Open Patent Publication No. 2-31467 describes a method in which the floating gate is formed of a non-doped poly-Si film. In this prior art, the poly-Si film has a large thickness of 250 nm, so that the voltage drop at the floating gate is large. Thus, the voltage required for the writing and erasing for the memory cell is increased. Even if the poly-Si film is oxidized for growing grains, the following problem arises.
In the poly-Si film, there are many interface states in the grain boundary. Its average density is more than 10.sup.17 /cm.sup.3. Accordingly, if a weak electric field of about 3 MV/cm is applied to the surface of the floating gate, for example, a depletion layer having a thickness of 60 nm or more is generated in the floating gate surface, and a voltage drop of several voltages or more occurs. As a result, it is necessary to apply an excess voltage corresponding to the voltage drop to the control gate. As described above, the use of such a thick non-doped poly-Si film as the floating gate in a flash memory, an EPPROM, or the like complicates the construction of the power supply section of the peripheral portion, and causes the consumed power to increase. As an example, if the floating gate is formed of a non-doped single crystal silicon film, the floating gate itself is depleted, so that there occurs a voltage drop of about 25 V.